1. Field of the Invention
The present invention relates to an output buffer circuit, and in particular, to a high voltage output buffer circuit that is connected between a low-breakdown-voltage circuit and a high voltage circuit in order to input an output signal from a low-breakdown-voltage circuit to a high-voltage circuit operating at a high voltage.
2. Description of the Related Art
Output buffer circuits are used to transfer low-voltage control signals to high-voltage circuits operating at a high voltage, where a pull-up transistor and a pull-down transistor are connected in series (totem-pole connection) (see, for example, Japanese Patent Laid-Open No. 2004-227753). In this case, while the pull-down transistor may be directly driven by a low-voltage control signal, controlling the pull-up transistor requires increasing the voltage of a low-voltage control signal with a level shifter before inputting.
The output buffer circuit of this type involves a large amount of gate-to-drain parasitic capacitance in the pull-up transistor, which would lead to difficulties in increasing switching rate while reducing the associated power consumption.